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Sharky Extreme : News From Inside The Industry October 26, 2007

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    By Vangie Beal :  May 2, 2002

    (Press Release) At the Embedded Processor Forum (EPF), the annual conference for developers of embedded microprocessors held this week, much of the attention was directed toward higher performance products, as evidenced by several product announcements, events and awards that focused on the high-performance, low-power 32- and 64-bit MIPS architectures, MIPS Technologies, Inc. announced today. MIPS Technologies Chairman and CEO John Bourgoin kicked off the conference with a keynote speech on the trend toward higher performance, cost-efficient embedded processors; a trend reflected by a number of MIPS-based product announcements. For example:

    • MIPS Technologies introduced a 32-bit core designed to optimize multi-CPU SOCs, which address the rapidly increasing bandwidth requirements in broadband and networking devices. Details on the MIPS32 M4K core were presented at EPF's High Performance Embedded Processors panel session.
    • AMD announced it has taken a license for the MIPS64 architecture, which it plans to use to develop 64-bit processors, in addition to its current product line of MIPS32-based processors, targeting personal connectivity devices.
    • NEC Corp. and its wholly owned subsidiary in the United States, NEC Electronics Inc., launched the 64-bit, MIPS-based VR7701 high-performance, integrated system processor, the first in its new VR7700 family of integrated processors. The VR7701 processor is an ideal solution for many demanding Internet applications.
    • Intrinsity, Inc. introduced its FastMATH Adaptive Signal Processor chip, which combines an innovative MIPS-based architecture with 2-GHz speeds, delivering unprecedented real-time signal-processing performance in applications that would otherwise require banks of DSPs, expensive FPGAs or power-hungry desktop CPUs. The company also announced the 2-GHz FastMIPS high-performance embedded processor. Both processors are based on the 32-bit MIPS32 architecture.
    • Micron Technology, Inc. performed a technology demonstration of its new SC1 processor, which combines a high-performance MIPS-based RISC processor subsystem with eight megabytes of embedded DRAM and application-specific IP, creating a platform for a range of innovative new designs.
    • QuickLogic Corp. and First Silicon Solutions (FS2) announced the availability of a real-time trace system analyzer for the QuickMIPS development platform. By delivering concurrent hardware and software debug, the FS2 System Analyzer for QuickMIPS speeds overall system designs and gives engineers added flexibility.

    Dr. John Mashey, a MIPS CPU pioneer now with venture capital firm Sensei Partners, joined executives from AMD, Broadcom, Intrinsity, Micron Technology, NEC, PMC-Sierra and QuickLogic -- all MIPS Technologies licensees -- to discuss major technology trends. The roundtable discussion was moderated by Markus Levy, senior analyst at In-Stat/MDR and president of the EEMBC benchmark consortium, and Keith Diefendorff, vice president of product strategy at MIPS Technologies.

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