The HyperTransport Technology Consortium -- the industry alliance behind the high-speed, chip-to-chip interconnect used in products ranging from AMD's Athlon 64 and Opteron and Transmeta's Efficeon processors to Nvidia's nForce chipsets and Microsoft's XBox -- has released the HyperTransport Release 2.0 specification. Fully backward-compatible with previous versions of the HyperTransport electrical specifications, the revised roadmap adds three faster bus speeds -- extending the 1.6 gigatransfers per second capability of HyperTransport 1.1 to 2.0, 2.4, and 2.8 GT/sec, using dual-data-rate clocks of 1.0, 1.2, and 1.4GHz respectively (versus the 800MHz double-pumped clock of the original spec).

The new peak rate delivers a maximum aggregate bandwidth of 22.4 gigabytes per second, 75 percent more than first-generation HyperTransport. The Release 2.0 standard also introduces mapping to PCI Express, the increasingly popular new I/O interconnect. Its packet-based data protocol format eliminates many sideband (control and command) signals while maintaining software compatibility with legacy PCI technologies.