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Sharky Extreme : News From Inside The Industry October 9, 2007

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    February 8, 2005

    It's still at least a year away from retail products -- the best-known of which by far will be the PlayStation3 game console -- but the team of Sony Corp., Sony Computer Entertainment Inc., IBM, and Toshiba Corp. has released a few more details about its forthcoming "Cell" processor, dubbed a "supercomputer on a chip." A multicore chip built for massive floating-point processing, the Cell combines a 64-bit IBM Power core -- itself capable of handling two threads simultaneously -- with eight "synergistic processing elements," each of which has its own 128-bit registers, integer and floating-point units, and 256K of cache. Add the control-center or traffic-cop Power core's own 32K of Level 1 and 512K of Level 2 cache, and you get more than 2.5MB of on-chip memory. The 90-nanometer-process SOI prototype displayed at the International Solid State Circuits Conference in San Francisco yesterday contains 234 million transistors and measures 221mm square.

    To keep 10 threads flowing at the same time, the Cell relies on ultra-high-bandwidth, built-in memory and input/output controllers that use Rambus Inc.'s XDR and FlexIO bus interfaces, respectively. XDR is an octal-data-rate memory interface that runs at 3.2GHz while the FlexIO (formerly codenamed Redwood) bus runs at 6.4GHz, helping deliver what Rambus calls an aggregate processor I/O bandwidth of approximately 100GB/sec. The Cell partners say initial hardware testing has yielded clock speeds north of 4.0GHz and performance in excess of 256 gigaflops (billion calculations per second). The processor can support multiple operating systems simultaneously, and is designed to combine its own multithreading with vast-scale parallel processing -- its programming model incorporates grid-computing-style transmission and execution of applications as well as data over broadband networks.

    Related Links: Sony, IBM, Toshiba, Rambus

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